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Y-C Picture-in-Picture (PIP) Controller
The MC44462 Y-C PIP controller is a low cost member of a family of high performance PIP controllers and video signal processors for television. It is a follow-up to the MC44461 PIP and has a modified input selection to allow higher performance in TV systems which have S-Video inputs on the back panel. The S-Video input is separate luma (luminance) and chroma components. It is NTSC compatible and contains all the analog signal processing, control logic and memory necessary to provide for the overlay of a small picture from a second non synchronized source onto the main picture of a television. All control and setup of the MC44462 is via a standard two pin I2C bus interface. The device is fabricated using BICMOS technology. It is available in a 56-pin shrink dip (SDIP) package. The main features of the MC44462 are:
MC44462
Y-C PICTURE-IN-PICTURE (PIP) CONTROLLER
SEMICONDUCTOR TECHNICAL DATA
* * * * * * * * * * * * * *
Switchable PIP Composite Video Signals - Video 1 and Video 2 S-Video Output Allows High Performance in TV Two PIP Sizes; 1/16 and 1/9 Screen Area
56
Freeze Field Feature Variable PIP Position in 64-X by 64-Y Steps PIP Border with Programmable Color Programmable PIP Tint and Saturation Control Automatic Main to PIP Contrast Balance Vertical Filter Integrated 64 k Bit DRAM Memory Resulting in Minimal RFI Minimal RFI Allows Simple Low Cost Application into TV I2C Bus Control - No External Variable Adjustments Needed Operates from a Single 5.0 V Supply Economical 56-Pin Shrink DIP Package
Device MC44462B
1
B SUFFIX PLASTIC PACKAGE CASE 859 (SDIP)
ORDERING INFORMATION
Operating Temperature Range TJ = -65 to +150C Package SDIP
YC-PIP System Diagram
CV Tuner/IF Cable Y C
Comb Filter (MC141625)
Y C
S W IIC M T R X Ymain in Cmain in YC PIP MC44462 CV1 CV2 IIC
CV Main
(unused) Video Processor Ymain out Cmain out Yin Cin R G B
Back Panel S-VHS Inputs Back Panel Composite Video Input
CV
This document contains information on a product under development. Motorola reserves the right to change or discontinue thisIC DEVICE DATA MOTOROLA ANALOG product without notice.
(c) Motorola, Inc. 1996
Issue 2
1
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ANALOG TO DIGITAL CONVERTER VERTICAL TIMEBASE HORIZONTAL TIMEBASE VIDEO POWER SUPPLY
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS (VCC = VDD = 5.0 V, TA = 25C, unless otherwise noted.)
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NOTE:
Sample Clock Frequency (4/3 FSC)
ADC - U, V Frequency Response @ -5.0 dB
ADC - Y Frequency Response @ -5.0 dB
Differential Non-Linearity
Integral Non-Linearity
Resolution
Vertical Sync Integration Time
Vertical Countdown Window
Burst Gate Width
Burst Gate Timing (from Trailing Edge Hsync, Pin 24)
HPLL Jitter
HPLL Pull-In Range
Free Run HPLL Frequency (Pin 16)
Output Impedance
Video Crosstalk (@ 75% Color Bars) Main to PIP PIP to Main
Color Bar Accuracy
Video Frequency Response (Main Video to -1.0 dB)
Video Gain
Video Output DC Level (Sync Tip)
Luma Output (Pin 49, Unterminated)
Composite Video Input (Pin 34 or 36)
Total Supply (Pins 8, 15, 43 and 50)
Junction Temperature (Storage and Operating)
Power Dissipation Maximum Power Dissipation @ 70C Thermal Resistance, Junction-to-Air
Output Current
Input Voltage Range
Power Supply Voltage
Power Supply Voltage
2
ESD data available upon request.
Rating
Characteristic
Symbol
PD RJA TJ
VCC
VDD
VIR
IO
MC44462
-65 to +150
-0.5 to +6.0
-0.5 to +6.0
-0.5, VDD + 0.5
Value
160
1.3 59
Total ISupply
Symbol
CVi
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
W C/W
Unit
mA
C
V
V
V
MOTOROLA ANALOG IC DEVICE DATA
Min - - - - - - - - - - - - - - - - - - - - - - - 232 - 296 15734 +2/-1 4.773 400 4.0 4.0 Typ 200 100 1.0 4.0 1.0 5.0 6.0 1.0 2.0 1.0 31 55 55 10 1 6 Max 160 - - - - - - - - - - - - - - - - - - - - - - H lines MHz MHz MHz Unit LSB LSB Vpp Vpp Vdc Bits deg mA Hz Hz dB dB s s s ns kHz
MC44462
ELECTRICAL CHARACTERISTICS (continued) (VCC = VDD = 5.0 V, TA = 25C, unless otherwise noted.)
Characteristic DIGITAL TO ANALOG CONVERTER Resolution Symbol Min Typ Max Unit
Y NTSC Decoder PIP Switch 0 90 4X S/C Osc + PLL 14.32 MHz 16X S/C Osc + PLL Clamp YUV V U 57.28 MHz
YUV Clamp
Multiplexer
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- - - - - - - - - - - 6 - - - - Bits Integral Non-Linearity 1 LSB LSB Deg dB Differential Non-Linearity +2/-1 10 Tint DAC Control Range (in 64 Steps) Saturation DAC Control Range (in 64 steps) 6.0 NTSC DECODER Color Kill Threshold - - - - - - -24/-16 1.0 0.5 - - - dB dB dB Threshold Hysteresis ACC (Chroma Amplitude Change, +3.0 dB to -12 dB) PIP CHARACTERISTICS PIP Size 1/9 Screen Horizontal 1/9 Screen Vertical 1/16 Screen Horizontal 1/16 Screen Vertical Border Size Horizontal Border Size Vertical - - - - - - - - - - 114 71 84 53 3 2 - - - - - - - - - pels lines pels lines pels - - - - - lines Output PEL Clock (4 FSC) 14.318 100 100 MHz % % Position Control Range Horizontal (% of Main Picture), 64 Steps Position Control Range Vertical (% of Main Picture), 64 Steps
Figure 1. Representative Block Diagram
Filter PLL 33 Decoder Clamp Caps 40 41 42
36 Video 1/ Luma 34 Video 2/Chroma 29 Y Main 32 C Main 37 Decoder ACC 49 Y Out 51 C Out 38 Decoder Xtal 39 Decoder PLL 7 16 FSC PLL 44 Encoder Phase 45 Encoder ACC 0
Input Switch
Low Pass Filter Band Pass Filter
Filter Tracking
H and V Timebase
28 31
Sync Sep H PLL
Y V U
6-Bit ADC 3 6
6
Tint DAC Sat DAC
Vert 6 6
Digital Logic
1 2 3 4 5 10 30
Hin Vin SCL SDA Reset Vid 1/2 Sel Multi Test
NTSC Encoder 90 4X S/C Osc + PLL
3.0 MHz LPF 3.0 MHz LPF 3.0 MHz LPF
U DAC V DAC Y DAC 6 6
Memory 8.0 k x 8 DRAM
46 Encoder PLL
47
52 53 54
Encoder Encoder Clamp Caps Xtal
This device contains approximately 500,000 active transistors.
MOTOROLA ANALOG IC DEVICE DATA
3
MC44462
Figure 2. Application Circuit
5.0 V 5.0 V
Horiz In Vert In I2C Ser Cl I2C Ser Data 5.0 V
1.0 k 1.0 k 1.0 k 1.0 k
1
470 k 2.2 F
2 3 4 5 6
Hin Vin SCL SDA Reset N/C 16 FSC Filter VDD (dig) VSS (dig)
MC44462
N/C N/C
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
0.01 0.01 0.01 0.01 10 F 75 Chroma Output 75 100 k X3 0.1 0.01 0.01 0.01 0.01 0.01 68 k 0.068 0.22 X2 12 0.1 0.1 Main Chroma Input Main Luma Input 75 Video 1/ Luma Input 2700 10 F 5.0 V 12 1000 0.1 5.0 V Luma Output
Encoder V Cap Encoder U Cap Endoder Y Cap C Out Video Out VCC Y Out Analog Gnd Encoder Xtal Encoder PLL Encoder ACC Encoder Phase Analog VCC Decoder V Cap Decoder U Cap Decoder Y Cap Decoder PLL Decoder Xtal Decoder ACC V1/YPIP Analog Gnd V2/CPIP Filter PLL C Main H PLL Multi Test Y Main
100 1000 5.0 V 10 F 100 0.01
7 8 9 10 11
Video 1/2 Select N/C N/C N/C VDD (mem) VSS (mem) N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C SN Sep
Video 1/2 Select Out 5.0 V 10 F 0.01
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
0.01
Video 2/ Chroma Input 75
75
1.0 F
75
0.0068
12 k 1.0 F
X2 - 14.31818 MHz - Fox 143-20 or equivalent X3 - 14.31818 MHz - Fox 143-20 or equivalent
NOTE: For proper noise isolation, Power Supply Pins 8, 14, 43 and 50 should be bypassed by both high and low frequency capacitors. As a guideline, a 10 F in parallel with a 0.1 F at each supply pin is recommended.
4
MOTOROLA ANALOG IC DEVICE DATA
MC44462
I2C REGISTER DESCRIPTIONS
Base write address = 24h Base read address = 25h Read Register There are two active bits in the single read byte available from the MC44462 as follows: Test Mode/Main Vertical and Horizontal Polarity Register Sub-address = 03h
Internal Test Mode Register (ITM0-2) - D0-D2 Sets the Multi Test Pin output to provide one of several internal signals for test and production alignment. Also controls the test memory address counter.
Write Vertical Indicator (WVI0) - D7 When 0 indicates that the write operation specified by the last I2C command has been completed. PIP Sync Detect Bit (PSD0) - D1 When 0 indicates that the PIP video H pulses are present and the horizontal timebase oscillator is within acceptable limits.
Write Registers Read Start Position/Write Start Position Registers Sub-address = 00h
Write Raster Position Start Bits (WPS0-2) - D0-D2 Establishes the horizontal beginning of the PIP and its black level measurement gate. This beginning may be varied by approximately 3.0 s. The position of this pulse may be observed through the Multi Test Pin 30 (See Test Mode Register Sub-address 03h). Read Raster Position Bits (RPS0-3) - D4-D7 Establishes the clamp gate position for the black level reference for the main picture. This position may be varied by approximately 5.0 s. The position of this pulse may be observed through the Multi Test Pin 30 (See Test Mode Register Sub-address 03h).
Pip Switch Delay/Vertical Filter Register Sub-address = 01h
PIP Switch Delay Bits (PSD0-3) - D0-D3 Delays the start of PIP on time relative to the PIP picture. These bits are used to center the PIP border and PIP picture in the horizontal direction. Vertical Filter Bit (VFON) - D4 When the filter is activated (VFON = 1) a three line weighted average is taken to provide the data stored in the field memory.
Border Color Register Sub-address = 02h
Border Color Bits (BC0-2) - D0-D2 These Bits control the color of the border. Note that when using one of the saturated border colors it is possible to get objectionable dot crawl at the edge of the border in some TVs unless appropriate comb filtering is used in the TV circuitry.
BC (2:0) 000 001 010 011
Border Color
Black
White 70%
No Border (clear) No Border (clear) Blue
100 101 110 111
Green Red
White
MOTOROLA ANALOG IC DEVICE DATA
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ITM (2:0) 000 001 010 011 Multi-Test I/O and Function Input - Analog Test mode Input - Digital Test mode Output - Sync Detect Output - PIP Switch 100 101 110 111 Output - PIP H Detect Output - PIP V Detect Output - PIP Clamp Output - Main Clamp
Main vertical polarity select bit (MVP0) - D6 Selects polarity of active level of vertical reference input. 0 = positive going, 1 = negative going.
Main horizontal polarity select bit (MHP0) - D7 Selects polarity of active level of horizontal reference input. 0 = positive going, 1 = negative going.
PIP Freeze/PIP Size/Main and PIP Video Source Register Sub-address = 04h
PIP Freeze Bit (STIL0) - D4 When set to one, the most recently received field is continuously displayed until the freeze bit is cleared. PIP Size Bit (PSI90) - D5 Switches the PIP size between 1/16 main size (when 0) and 1/9 main size (when 1). Video Type Select Bit (YCPSEL) - D6 Selects which video type will be applied to the PIP input. PIP Video Source Select Bit (PSEL0) - D7 Selects which composite video input will be applied to the video decoder to provide the PIP video in CV mode.
AAAAAAAAAA A A AAAAAAAAAA A A AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AAAAAAA A AAAAAAAAAAAAAAAA AAAA A AAAAAAA AAAA
PSEL 0 0 1 YCPSELAAAAAAAAAA Function 1 0 YC Input to PIP CV1 Input to PIP CV2 Input to PIP
PIP On/PIP Blank Register Sub-address = 05h
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PIP On Bit (PON0) - D0 When on (1) turns the PIP on. PIP Blanking Bit (PBL0) - D4 When on (1) sets the PIP to black. If the PIP is off, then it will be black if it is turned on. Overrides all other settings of the PIP control.
PIP X Position Register Sub-address = 06h
X Position Bits (XPS0-5) - D0-D5 Moves the PIP start position from the left to the right edge of the display in 64 steps. There is protection circuitry
5
MC44462
to prevent the PIP from interfering with the main picture sync pulses. PIP Y Position Register Sub-address = 07h are matched. In addition to this, the tint of the PIP can be varied 10 in a total of 64 steps by changing the value of these bits to suit viewer preference. PIP Luma Delay Register Sub-address = 0Ah
Y Position Bits (YPS0-5) - D0-D5 Moves the PIP start position from the top to the bottom edge of the display in 64 steps. There is protection circuitry to prevent the PIP from interfering with the main picture sync pulses.
PIP Chroma Level Register Sub-address = 08h
Y Delay (YDL0-2) - D0-D2 Since the Chroma passes through a bandpass filter and the color decoder, it is delayed with respect to the Luma signal. Therefore, to time match the Luma and Chroma these bits are set to a single value determined to be correct in the application.
Pip Fill/Test Register Sub-address = 0Ch
Chroma (C0-5) - D0-D5 The color of the PIP can be adjusted to suit viewer preference by setting the value stored in these bits. A total of 64 steps varies the color from no color to maximum. This control acts in conjunction with the auto phase control.
PIP Tint Level Register Sub-address = 09h
PIP Fill Bits (PIPFILL0-1) - D0-D1 May be used to fill the PIP with one of three selectable solid colors Test Register Bits (INTC0 and MACR0) - D6-D7 Used for production test only.
Tint (T0-5) - D0-D5 An auto phase control compares the main color burst to the internally generated pseudo color burst so that the tints
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I2C REGISTER TABLE
Data Bit Sub- address 00 01 02 03 04 05 06 07 08 09 D7 D6 D5 D4 D3 - D2 D1 D0 RPS3 - - RPS2 - - RPS1 - - - RPS0 WPS2 PSD2 BC2 WPS1 PSD1 BC1 WPS0 PSD0 BC0 VFON - - PSD3 - - - - MHP0 MVP0 ITM2 - - ITM1 - - ITM0 - PSEL0 - - - - - - - - YCPSEL - - - - - - - - PSI90 - STIL0 PBL0 PON0 XPS0 YPS0 C0 T0 XPS5 YPS5 C5 T5 - - - XPS4 YPS4 C4 T4 - - - XPS3 YPS3 C3 T3 - - - XPS2 YPS2 C2 T2 XPS1 YPS1 C1 T1 0A 0B YDL2 - - YDL1 - - YDL0 - - 0C
6
MOTOROLA ANALOG IC DEVICE DATA
MC44462
OUTLINE DIMENSIONS
B SUFFIX PLASTIC PACKAGE CASE 859-01 (SDIP) ISSUE O
-A56 29
NOTES: 1. DIMENSIONS AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH. MAXIMUM MOLD FLASH 0.25 (0.010). INCHES MIN MAX 2.035 2.065 0.540 0.560 0.155 0.200 0.014 0.022 0.035 BSC 0.032 0.046 0.070 BSC 0.300 BSC 0.008 0.015 0.115 0.135 0.600 BSC 0 15 0.020 0.040 MILLIMETERS MIN MAX 51.69 52.45 13.72 14.22 3.94 5.08 0.36 0.56 0.89 BSC 0.81 1.17 1.778 BSC 7.62 BSC 0.20 0.38 2.92 3.43 15.24 BSC 0 15 0.51 1.02
-B1 28
L H C
-TSEATING PLANE
K F D 56 PL 0.25 (0.010) E
M
DIM A B C D E F G H J K L M N
G
N J 56 PL BS
M
TA
S
0.25 (0.010)
M
T
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 or 602-303-5454 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com
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MOTOROLA ANALOG IC DEVICE DATA
*MC44462/D*
MC44462/D
7

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